Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /ETH /ETH_MTL_TXQ0_UNDERFLOW

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Interpret as ETH_MTL_TXQ0_UNDERFLOW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0UFFRMCNT0 (Val_0x0)UFCNTOVF

UFCNTOVF=Val_0x0

Description

Queue 0 Underflow Counter Register

Fields

UFFRMCNT

Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. Access restriction applies. Clears on read. Self-set to 1 on internal event.

UFCNTOVF

Overflow Bit for Underflow Packet Counter This bit is set every time the Tx Queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. Access restriction applies. Clears on read. Self-set to 1 on internal event.

0 (Val_0x0): Overflow not detected for underflow packet counter

1 (Val_0x1): Overflow detected for underflow packet counter

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